Chapter 1 Sequence Detector 1.1 Aim To build an FSM that would detect the pattern 101 that has arrived over past 3 clock cycles, one bit a time, over a single bit input port. 1.2 State Diagram 1.3 Verilog module moore_101_detector (w, rst, clk, y ); input w, rst, clk; output y; reg y; parameter [1:0] stRESET = 0, stGOT1 = 1,stGOT10 = 2, stGOT101 = 3; reg [1:0] state; always @ ( posedge clk ) begin if (rst) state

 
 

Chapter 1 Sequence Detector 1.1 Aim To build an FSM that would detect the pattern 101 that has arrived over past 3 clock cycles, one bit a time, over a single bit input port. 1.2 State Diagram 1.3 Verilog module moore_101_detector (w, rst, clk, y ); input w, rst, clk; output y; reg y; parameter [1:0] stRESET = 0, stGOT1 = 1,stGOT10 = 2, stGOT101 = 3; reg [1:0] state; always @ ( posedge clk ) begin if (rst) state <= stRESET; else begin case ( state ) stRESET: begin if ( w==1’b1 ) state <= stGOT1 ; else state <= stRESET; end stGOT1: begin if ( w==1’b0 ) state <= stGOT10; else state <= stGOT1; end stGOT10: begin if ( w==1’b1 ) state <= stGOT101; else state <= stRESET; end stGOT101: begin if ( w==1’b1 ) state <= stGOT1; else state <= stGOT10; end default: state <= stRESET; // Only for illegal input ( ?? ) // Legal inputs would not bring FSM here. endcase end end // Moore output logic // ( combinational function of just “state” ) always @( * ) begin case ( state ) stRESET : y = 0; stGOT1 : y = 0; stGOT10 : y = 0; stGOT101 : y = 1; default : y = 0; endcase end endmodule 1.4 Procedure 1.5 Results A sample set of the verilog code, the input and output test vectors are provided in the dropdown box under Finite State Machines (Chapter 4) The input vectors are obtained as w rst 0 1 1 0 0 0 1 0 1 0 The output vectors are obtained as y 0 0 0 0 1

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